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IHP-GmbH/IHP-Open-ADK

IHP Open ADK 0.2.0 documentation

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IHP Open Assembly Design Kit

IHP-GmbH/IHP-Open-ADK

Quickstart
Introduction
- What the ADK is
  - The role model
  - The abstraction boundary
  - Where assembly verification sits
    
    The geometric axis: assembly DRC
    
    The connectivity axis: assembly LVS
  - What the ADK is not
  - Where the boundary comes from
  - A note on maturity
- The gap it closes
- The ecosystem
- Glossary
Installation
- The ADK-Tools image
- Installing on the host
- Environment and path discovery
  - The discovery chain
  - The variables
  - Marker subpaths and accepted directory names
  - Where the walk starts
  - Two lookups have their own shape
    
    The worker interpreter
    
    The ADK runner, seen from the plugin
  - Fail loud, do not degrade
  - ${VAR} references in path inputs
  - Setting the environment
  - See also
The assembly flow
- Overview
- From die GDS to KiCad
  - What you are producing
  - Step 1: look at the GDS before converting it
  - Step 2: say where the pads are
  - Step 3: curate the pads
  - Step 4: generate the footprint
    
    Pad numbers are pad names
  - Step 5: generate the symbol
  - A die with no GDS
  - Interposer I/O pads
  - Traceability properties
  - Checking the result
  - Next
- Designing the interposer
- Exporting the assembly
- Generating the assembly GDS
  - What the converter consumes
  - What it produces
  - Running it
  - From KiCad routing to fabrication geometry
    
    Copper layers must be named after the process metals
    
    Traces, arcs and the outline
    
    Vias come from the base PDK’s own PCells
  - Cu pillars and bumps
    
    Why a missing interposer PDK is fatal here
  - Flip-chip placement
  - Sidecars written alongside the GDS
    
    Boundary manifest
    
    Pillar manifest
    
    Optional boundary annotation
  - After the conversion
- Verification stages
- Viewing and inspecting
  - Opening the assembly in Chiplet Studio
    
    How the file resolves its layouts
    
    What the panels give you
    
    Drilling down into a component’s layout
    
    Other panels
  - Opening the GDS in KLayout with named layers
  - Walking DRC violations in the Marker Browser
  - Viewing chiplet boundaries
  - Related pages
- Reference design
The Assembly Design Kit
- Architecture
- Adapter contract
  - Interposer adapter
    
    Location and selection
    
    Shipped interposer adapters
    
    Required abstract inputs
    
    Optional rule-parameter overrides
    
    What interposer adapters must NOT do
  - Interconnect adapter
    
    Selecting an interconnect adapter
    
    Shipped interconnect adapters
    
    The parameter pack
    
    Optional region narrowing
    
    What interconnect adapters must NOT do
    
    Per-method refinement
  - Evolving the contract
  - Writing an adapter for a new interposer
- Placement rules (ASM)
- Interconnect rules (IXN)
- Running the assembly DRC
- KiCad DRU generation
- OpenROAD 3Dblox export
- Pad to pillar alignment
  - Inputs
    
    Extracting pads from a GDS
  - The transform
  - Matching
    
    Findings
    
    Auto-resolve demotion
    
    Tolerance
  - Running the check
    
    The JSON report
    
    --strict
    
    Exit codes
  - Importable entry points
- Registries and schemas
  - Version discipline
  - config/rule_params.json
  - config/interconnect.json
  - config/layers.json
  - config/chiplet_pads.json
  - Registry schemas
    
    Rule parameter registry
    
    Interconnect registry
    
    Layer registry
  - Sidecar schemas
  - Changing a registry
Formats and contracts
- The .chiplet assembly file
  - What the format is for
    
    Relationship to CDXML, JEP30 and 3Dblox
  - File structure
  - The assembly block
  - The technologies block
  - The connection_stacks block
  - Paths and the ${VAR} convention
  - Validation rules
  - Reading and writing .chiplet files
    
    Implementer rights
  - Where to go next
- Components and optional blocks
  - The components block
    
    Geometry: position, dimensions and anchor
    
    orientation
    
    connection and per-die z-mounting
    
    The interposer attachment_surface_z
    
    io_pads
    
    die_array
  - Optional blocks
    
    interconnect
    
    interfaces
    
    netlist
    
    flow
    
    _metadata and intermediate files
    
    Proposed extensions: cdxml_ref and 3dblox_ref
  - A complete example
  - Where to go next
- Coordinate frames
  - The rules in brief
  - The canonical frame
    
    Why the GDS bbox corner
  - Position semantics
    
    Interposer dimensions against interposer position
  - The anchor convention
  - Orientation and flip-chip mirroring
  - From a die-local coordinate to an assembly coordinate
    
    Worked case
    
    The 3D world frame
  - The z-mounting rule
    
    How the mounting surface resolves
    
    Worked case, two dies and two methods
    
    Edge cases
  - io_pads
  - The leak guard
  - The writer contract
    
    Why KiCad needs a finalizer
  - The reader contract
  - Verification fixtures
  - Appendix: glossary of coordinate frames
  - Where to go next
- Boundary manifest
  - File location and auto-discovery
  - Producers and consumers
  - Schema
    
    Top level
    
    Boundary entries
    
    Which fields are authoritative
    
    Vestigial fields
  - No z coordinate: single tier by design
    
    The schema file
  - Version policy
  - Why the boundary left the fabrication layer namespace
    
    The legacy path
  - Example
- Pillar manifest
  - File location
  - Producers and consumers
  - Schema
    
    Top level
    
    Pillar entries
    
    The schema file
  - Frame and semantics
    
    As drawn, not as requested
    
    The canonical frame
    
    Auto-resolve bookkeeping
  - Version policy
  - Example
  - Using it
- Interconnect methods manifest
- Pin lists
  - Shape
    
    Metadata
    
    Pin entries
    
    Coordinate frame
  - How pin lists are produced
    
    From a die GDS
    
    From a KiCad footprint
    
    The dbu_um caveat
  - What the ADK consumers read
    
    Consumer 1: bump maps for the 3Dblox export
    
    Consumer 2: pad positions for the alignment check
- 3Dblox interoperability
  - What 3Dblox is
  - The shared core
  - Forward mapping, .chiplet to 3Dblox
  - What does not map, and why
    
    Dropped by declaration
    
    Not expressible in .chiplet v1.0
    
    External inputs an export needs
  - Conventions that a naive converter gets wrong
    
    Connection thickness is the stack height, exactly
    
    The attachment surface is not the maximum z
    
    Flip is a mounting intent, not a shared mirror convention
    
    Physical thickness has one source
  - The reverse direction
  - The 3dblox_ref proposed extension
  - One assembly, one authoritative placement source
  - The exporter in the ADK
Supported tools
- KiCad ADK fork
  - Why a fork
  - The delta versus upstream
    
    Geometry limits
    
    Units and grids
    
    Rendering at extreme zoom
    
    Integer arithmetic
    
    Zone filling
    
    Export precision, HyperLynx
    
    Export precision, chiplet
    
    Python surface
    
    Stability
  - Where the exports live in the UI
  - How it is built and pinned
  - What this page does not assert
- Chiplet export plugin
  - What one run produces
  - Reaching it
  - What the dialog controls
    
    Output directory
    
    Outputs
    
    PDK roots
    
    Pipeline options
    
    Per-die settings
    
    Assembly DRC
  - The orchestrator
    
    The sequence
    
    Turning a design into runner flags
    
    The two adapter axes
  - Boundaries: manifest, not layer
  - Headless use
  - Writer parity
  - Troubleshooting
- gds2kicad
  - The problem it solves
  - Installing
  - Telling it where the pads are
    
    The role of the .lyp
  - Die to footprint
    
    Pad extraction
    
    Traceability properties
  - Die to symbol
  - The pin list
  - Curating pads by hand
  - Database units
  - Black-box chiplets
  - Interposer I/O pads
  - Board back to chiplet netlist
  - The GUIs
  - Where files are written
  - Troubleshooting
- Chiplet Studio
  - What it is for
  - Opening an assembly
    
    Importing a bare GDS
  - The 3D view
    
    Render modes
    
    Black-box chiplets
  - Layer stackups
    
    Attachment bodies
  - The 2D drill-down
  - The net graph
  - The flow pipeline
  - Python scripting
  - Running the application
  - Resolving PDK roots
  - Known limits
- Interposer PDK (OpenIntM4TM2)
  - The process
    
    The metal stack
  - The KLayout technology
    
    How many layers
  - DRC
    
    The decks
    
    Rule values
    
    Testing
  - LVS
  - The PCell library
  - Cu-pillar generation
  - The KiCad side
    
    The board template
    
    Device footprints and symbols
  - What INTERPOSER_PDK_ROOT provides
  - Simulation and extraction support
- Interconnect PDK
  - Why this is a separate PDK
  - The method registry
  - Shipped methods
    
    Parameters per method
    
    Fabrication anchors
  - The 3D auxiliary layers
  - The generators
    
    Bump bodies
    
    Bump macros for OpenROAD
  - 3D stackup fragments
  - The standalone DRC deck
  - Relationship to the ADK
  - What INTERCONNECT_PDK_ROOT provides
- The ADK-Tools image
Roadmap
- ADK domains
- Analysis and automation
- The connectivity axis of assembly verification
Contributing
- Contributing to the ADK
- Contributing to this documentation
References
- Project resources
- Bibliography

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